Integrated circuits are the backbone of computers and most modern consumer electronics. In a typical integrated circuit fabrication, various semiconductor materials are formed into ingots typically comprised of nearly pure silicon, then sliced into wafers. Each wafer is typically processed through deposition, removal, patterning, and/or modification of electrical properties such that a plurality of dies are formed on the wafer. The dies are generally cut from the wafer, placed in packages, wired to pins of the package, and sealed, resulting in individual integrated circuits. During the fabrication of the integrated circuits, the wafers and dies are often tested after various processing steps to determine if the wafer has been damaged and/or to determine if the dies function properly. However, these tests are typically optimized by the fabricator to test the functionality of each die rather than their tolerances. As such, further testing of the integrated circuits is required to determine whether the integrated circuits can withstand real-world conditions.
Despite advances in technology and power systems, integrated circuits often experience inputs (typically called “transients”), whether on power, input, output, or input/output (“I/O”) pins, that can cause unexpected functionality, errors, failure, or even destruction of components of integrated circuits. These transients generally include electrostatic discharge, voltage spikes, voltage drops, current spikes, current drops, electromagnetic radiation, and other electrical noise. Integrated circuits are generally designed to withstand some amount of these transients such that the transients neither produce erroneous results, nor cause failure of the integrated circuit, as the circuit continues to operate.
After fabrication and production of a batch of integrated circuits is complete, a subset of the integrated circuits are typically removed and undergo transient testing to determine a baseline of transient responses for the batch (i.e., whether the subset of integrated circuits output erroneous results or are destroyed by the transients). Typically, a first set of these “test” integrated circuits undergo tests for electrical overstress (EOS) or other electrostatic discharge (ESD), while a second set of test integrated circuits undergo tests for transient induced latch-up (TLU). In some circumstances, a third set of test integrated circuits undergo tests for electrical fast transients (EFT) and a fourth set of test integrated circuits undergo tests for radiated immunity (RI). An EOS test generally includes causing a sudden and momentary increase of power (for example, electrical current) on one pin of an integrated circuit (typically a power pin) then determining if any of the semiconductor materials from which the integrated circuit is made have been damaged. A TLU test generally includes causing a spike of positive or negative voltage on one pin of an integrated circuit to determine if a low-input impedance path has been inadvertently created between the power supply of the integrated circuit and ground. An EFT test generally includes causing a high frequency disturbance on one input/output pin of an integrated circuit to determine if an undesired operating mode has been created. A RI test generally includes exposing an integrated circuit to radiated electromagnetic energy while it is running to determine if the integrated circuit continues to operate without any degradation of performance. Generally, a batch of integrated circuits is tested only to determine their responses to the EOS and TLU tests.
Conventional tests for EOS and TLU generally require different testing methodologies and implementations. EOS testing requires that a sudden and momentary increase of power be transferred to a power supply pin of the integrated circuit. Conventional EOS test implementations typically include at least one capacitor that is switched from a charging mode to a discharge mode, thereby discharging into the integrated circuit. However, this EOS testing implementation is crude and often results in wild fluctuations in the power stored by the capacitor as well as excess leakage current through the capacitor. This method requires an increased time to charge the capacitor for each EOS test, ignores the properties of real world spikes that are experienced by integrated circuits (i.e., the discharge is often much larger than those experienced by integrated circuits in the real world), and often destroys the integrated circuit because the spike of power is typically too difficult to finely control. Furthermore, the EOS test signal may not have sufficient duration to effectively test for EOS characteristics of the integrated circuit. For example, conventional EOS testing may partially damage the integrated circuit, resulting in an integrated circuit that may operate normally under normal conditions, yet exhibit erroneous operation outside of normal conditions. Because a subset of a completed batch integrated circuits are used to indicate the viability of the entire batch, partially damaged integrated circuits typically indicate false positives, resulting in defective integrated circuits being marketed and sold.
TLU testing, on the other hand, generally requires that a spike of positive or negative voltage be sustained for a longer period of time than the sudden and momentary power increase of the EOS testing to trigger a parasitic structure of a component of the integrated circuit that acts as a short circuit, and thus creates the low-impedance path. In this manner, conventional TLU test implementations typically use separate pulse generation circuits and pulse amplification circuits. However, TLU testing implementation is generally costly, time consuming, and requires additional considerations of the noise effects on the TLU testing signal from the circuitry in the pulse generation circuits and pulse amplification circuits.
Testing costs, methodologies, and implementations to test EOS and TLU characteristics of integrated devices are increased because EOS and TLU testing often require different test signal circuits, different ways to test the integrated circuits, and different implementations, all the while ignoring real world conditions that may be experienced by the integrated devices. Moreover, EOS and TLU testing is often time consuming and laborious when more than one pin of an integrated circuit is tested, requiring constant readjustment of the integrated circuit and relocation of hardware, circuitry, measurement, and/or other test equipment to perform the tests. Consequently, there is a continuing need for accuracy in EOS and TLU testing of an integrated circuit, and particularly a continuing need to quickly and efficiently test both the EOS and TLU characteristics of an integrated circuit.